H / O

Interface Classification

I / O interface function is responsible for implementing the CPU through the system bus to link the I / O circuit and the peripheral device, according to the complexity of the circuit and equipment, I / O Interface hardware is mainly divided into two categories:

(1) I / O interface chip

Most of these chips are integrated, entered different commands and parameters through the CPU, and Control-related I / O circuits and simple peripherals work accordingly, common interface chips such as timing counters, interrupt controllers, DMA controllers, parallel interfaces, and the like.

(2) I / O Interface Control Card

By a certain logical group by several integrated circuits, or directly with the CPU on the motherboard, or a plugin Plug in the system bus slot.

According to the connection object of the interface, they can be divided into a serial interface, a parallel interface, a keyboard interface, and a disk interface.

Interface function

Due to a wide variety of peripherals of the computer, the electromechanical transmission device is used, and therefore, the CPU has the following problems when data exchange with the I / O device: < / p>

speed mismatch: I / O device's operating speed is slower than the CPU, and due to the difference in species, the speed difference between them is also very large, such as the transfer speed of the hard disk is faster than the printer. a lot of.

timing does not match: Each I / O device has its own timing control circuit, transmitting data at its own speed, and cannot be unified with the timing of the CPU.

Information format does not match: Different I / O device stores and processing information differently, for example, two types of serial and parallel; can also be divided into binary format, ASCII coding, and BCD coding, etc. .

Information type does not match: the signal types used in different I / O devices are different, and some are digital signals, and some are analog signals, so the processing methods used are also different.

Based on the above reasons, data exchange between CPUs and peripherals must be completed by an interface. The usual interface has some functions:

(1) Setting data storage, buffer logic To accommodate the speed difference between the CPU and the peripheral, the interface is usually composed of some registers or RAM chips, and if the chip is sufficiently large, the transmission of bulk data can be realized;

(2) can perform information format Conversion, such as serial and parallel conversion;

(3) can coordinate the difference between the type and level of the CPU and the outside, such as level conversion drivers, digital mode or modulus conversion Wait;

(4) Coordination timing difference;

(5) address decoding and device selection function;

(6) Set interrupt and DMA control Logic to ensure that interrupts and DMA request signals are generated in the case of interrupt and DMA allowed, and interrupt processing and DMA transmission are completed after accepting an interrupt and DMA response.

Control mode

CPU has the following ways to control the external configuration:

(1) program query mode

In this way, the CPU is inquired by the I / O instruction to specify the current state of the peripheral, if the peripheral is ready, the input or output of the data is performed, otherwise the CPU waits, the cycle query.

The advantage of this way is that the structure is simple, only a small amount of hardware circuit is required, and the disadvantage is that the CPU is much higher than the peripheral, and therefore, it is usually waiting state, the working efficiency is very low.

(2) Interrupt processing mode

In this manner, the CPU is no longer passive, but can perform other programs. Once the peripheral is ready for data exchange, it can be proposed to the CPU. Service request, CPU If you respond to request, you temporarily stop the execution of the current program, turn the executive program corresponding to the request, and then continue to perform the original interrupted program.

The advantages of interrupt processing method is obvious, it not only saves the CPU to query peripheral states and waiting for peripherals, improve the work efficiency of the CPU, but also meets peripherals Real-time requirements. However, it is necessary to assign an interrupt request number and a corresponding interrupt service program for each I / O device. In addition, an interrupt controller (I / O interface chip) manages the interrupt request proposed by the I / O device, such as setting interrupt mask, Interrupt request priority, etc.

In addition, the disadvantage of the interrupt processing method is that every time it transmits a character, start the interrupt controller, but also retains and restores the site to continue the original procedure, the amount of work is very good. This makes it possible if you need a lot of data exchange, the system performance will be low.

(3) DMA (Direct Memory Access) transfer mode

The most obvious is that it is not a characteristic of DMA in software instead of using a dedicated controller to control the external memory and The data exchange between settings, no CPU intervention, greatly improves the work efficiency of the CPU.

Before performing DMA data transfer, the DMA controller will apply to the CPU application bus, and the CPU is allowed, and the control is handed over, and therefore, the bus control is powered by the DMA controller when data exchange. Mastering, after the transmission is over, the DMA controller puts the bus control right to the CPU.

(4) Channel mode

I / O device failure

The I / O device fault performance in the computer has the following three aspects:

to prevent I / O equipment failure: I / O equipment is a precision electronic product, the environment is strict in the use process, do not use in high temperatures, humid environments .

I / O process A CPU bottleneck

appears in a larger enumeration of a restricted CPU performance, the I / O process affects the workload. In the system restricted by the CPU, the batch process makes I / O performance worse. Usually, when the system priority is lowered, when the CPU is subject to bottleneck, the batch process is barely running I / O because of the resource competition for the online process. Every time I / O, a process begins to release the CPU resource and take over higher priority process. But even if the I / O process is complete, the batch process also needs to compete for the process resources that have completed the task, and accept the CPU thread scheduling. The online process can usually obtain the necessary CPU resources. The I / O process does not slow down the workload of the Customer Information Control System (CICS) or Information Management System (IMS) because each I / O does not synchronize. However, some special processes are affected by the CPU bottleneck as the batch. In CICS, once I / O completion transaction, I / O has passed the CICS chain scheduler before I / O continues to work. In CICS workload is especially obvious that I / O has a deep adjustment queue. Running Message Processing Area (MPR's) in the IMS transaction is taken with different paths, but all are the same work. Once the database I / O is completed, IMS will notify the MPR to compete for resources in it before it works more. The fastest I / O cannot be implemented. Therefore, the bottleneck in the environment in which the memory is prevented in the CPU-limited environment as much as possible. I / O inputs of memory include buffer pools, reference tables, data cache spaces, and other methods.