Control register

Coprocessor control bits in CR0

The 4 bits of CR0: extended type bit ET, task switching bit TS, emulation bit EM and math presence bit MP are used to control 80x86 floating point (Mathematics) The operation of the coprocessor. The ET bit (flag) of CR0 is used to select the protocol used to communicate with the coprocessor, that is, to indicate whether the 80387 or 80287 coprocessor is used in the system. The TS, MP, and EM bits are used to determine whether a floating-point instruction or a WAIT instruction should generate a Device Not Available (DNA) exception. This exception can be used to save and restore floating-point registers only for tasks that use floating-point operations. For tasks that do not use floating-point operations, doing so can speed up the switching operations between them.

ET

Bit 4 of CR0 is the extension type (Extension Type) flag. When the flag is 1, it indicates that there is an 80387 coprocessor in the system and the 32-bit coprocessor protocol is used. ET=0 indicates that the 80287 coprocessor is used. If the emulation bit EM=1, this bit will be ignored. During the processor reset operation, the ET bit will be initialized to indicate the type of coprocessor used in the system. If there is 80387 in the system, ET is set to 1, otherwise if there is an 80287 or there is no coprocessor, ET is set to 0.

TS

Bit 3 of CR0 is the Task Switched flag. This flag is used to postpone saving the content of the coprocessor during task switching until the new task starts to actually execute the coprocessor instructions. The processor sets this flag every time a task switches, and tests the flag when executing coprocessor instructions.

If the TS flag is set and the EM flag of CR0 is 0, a device non-existent exception will be generated before executing any coprocessor instructions. If the TS flag is set but the MP and EM flags of CR0 are not set, then no device non-existence exception will be generated before executing the coprocessor instruction WAIT/FWAIT. If the EM flag is set, the TS flag has no effect on the execution of the coprocessor instructions, as shown in Table 4-1.

Table 4-1 The influence of different combinations of flags EM, MP and TS in CR0 on the action of coprocessor instructions

0

0

0

During task switching, the processor does not automatically save the context of the coprocessor, but sets the TS flag. This flag will cause the processor to generate a device non-existent exception when encountering a coprocessor instruction at any time during the execution of a new task instruction stream. The processing program of the device without exception can use the CLTS instruction to clear the TS flag and save the context of the coprocessor. If the task has never used the coprocessor, then the corresponding coprocessor context does not need to be saved.

EM

Bit 2 of CR0 is the EMulation flag. When this bit is set, it means that the processor does not have an internal or external coprocessor, and the execution of the coprocessor instruction will cause the device to have no exception; when it is cleared, it means that the system has a coprocessor. Setting this flag can force all floating-point instructions to be simulated by software.

MP

Bit 1 of CR0 is the monitor coprocessor (Monitor coProcessor or Math Present) flag. It is used to control the interaction between WAIT/FWAIT instruction and TS mark. If MP=1, TS=1, then executing the WAIT instruction will produce a non-existent device exception; if MP=0, the TS flag will not affect the execution of WAIT.

The protection control bit in CR0

PE

Bit 0 of CR0 is the Protection Enable flag. When this bit is set, the protection mode is turned on; when it is reset, the real address mode is entered. This flag only enables segment-level protection, and does not enable the paging mechanism. To enable the paging mechanism, both PE and PG flags must be set.

PG

Bit 31 of CR0 is the paging flag. When this bit is set, the paging mechanism is enabled; when reset, the paging mechanism is disabled. At this time, all linear addresses are equivalent to physical addresses. The PE flag must be turned on or at the same time before turning on this flag. That is, to enable the paging mechanism, the PE and PG flags must be set.

WP

For Intel 80486 or above CPUs, bit 16 of CR0 is the Write Proctect flag. When this flag is set, the processor will prohibit the super user program (such as privilege level 0 program) to write to the user-level read-only page; when this bit is reset, the reverse is true. This flag is conducive to UNIX-like operating systems to implement Copy on Write technology when creating a process.

N

For Intel 80486 or above CPUs, bit 5 of CR0 is the coprocessor error (Numeric Error) flag. When this flag is set, the internal reporting mechanism of x87 coprocessor errors is enabled; if the flag is reset, the x87 coprocessor error reporting mechanism in the form of PC is used. When NE is in the reset state and the IGNNE input pin of the CPU has a signal, then the math coprocessor x87 error will be ignored. When NE is in the reset state and there is no signal at the IGNNE input pin of the CPU, then the unshielded math coprocessor x87 error will cause the processor to generate an external interrupt through the FERR pin, and execute the next waiting-form floating-point instruction Or stop instruction execution immediately before WAIT/FWAIT instruction. The FERR pin of the CPU is used to simulate the ERROR pin of the external coprocessor 80387, so it is usually connected to the input request pin of the interrupt controller. NE flag, IGNNE pin, and FERR pin are used to use external logic to implement an external error reporting mechanism in the form of a PC.

Enable the protected mode PE (Protected Enable) bit (bit 0) and turn on the paging PG (Paging) bit (bit 31) to control the segmentation and paging mechanism, respectively. PE is used to control the segmentation mechanism. If PE=1, the processor works in an environment with the segmentation mechanism turned on, that is, it runs in a protected mode. If PE=0, the processor turns off the segmentation mechanism and works in real address mode like 8086. PG is used to control the paging mechanism. If PG=1, the paging mechanism is turned on. If PG=0, the paging mechanism is disabled, and the linear address is used directly as the physical address.

If PE=0, PG=0, the processor works in real address mode; if PG=0, PE=1, the processor works in a protected mode without paging mechanism; if PG= 1. PE=0, at this time, because the paging mechanism cannot be enabled in the protected mode, the processor will generate a general protection exception, that is, this flag combination is invalid; if PG=1, PE=1, the processor is working Under the protected mode of the paging mechanism.

When changing the PE and PG bits, you must be careful. Only when at least part of the code and data of the executing program have the same address in the linear address space and the physical address space, we can change the setting of the PG bit. At this time, this part of the code with the same address acts as a bridge between the paged and unpaged worlds. Regardless of whether the paging mechanism is turned on, this part of the code has the same address. In addition, the page cache TLB must be refreshed before opening paging (PG=1).

After modifying the PE bit, the program must immediately use a jump instruction to refresh any instructions in the different modes that have been acquired in the processor execution pipeline. Before setting the PE bit, the program must initialize several system segments and control registers. When the system is first powered on, the processor is reset to PE=0 and PG=0 (that is, the real mode state) to allow the boot code to initialize these registers and data structures before enabling the segmentation and paging mechanism.

CR2 and CR3

CR2 and CR3 are used for paging mechanism. CR3 contains the physical address of the page of the page directory table, so CR3 is also called PDBR. Because the page directory table pages are page-aligned, only the upper 20 bits of this register are valid. The lower 12 bits are reserved for more advanced processors, so the lower 12 bits must be set to 0 when loading a new value into CR3.

Using the MOV instruction to load CR3 has the side effect of invalidating the page cache. In order to reduce the number of bus cycles required for address translation, the page directories and page tables accessed in recent days will be stored in the processor's page cache device. This buffer device is called Translation Lookaside Buffer (TLB). ). Only when the required page table entry is not included in the TLB, additional bus cycles will be used to read the page table entry from the memory.

Even if the PG bit in CR0 is in the reset state (PG=0), we can load CR3 first. To allow the paging mechanism to be initialized. When switching tasks, the content of CR3 will also change accordingly. But if the CR3 value of the new task is the same as that of the original task, the processor does not need to refresh the page cache. In this way, the task of sharing the page table can be performed faster.

CR2 is used to report error messages when a page exception occurs. When reporting a page exception, the processor will store the linear address that caused the exception in CR2. Therefore, the page exception handler in the operating system can determine which page in the linear address space caused the exception by checking the contents of CR2.